In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the output of each flip-flop is connected to the 'data' input of the next flip-flop in the chain, resulting in a circuit that shifts by one position the 'bit array' stored in it, 'shifting in' the data present at its input and 'shifting out' the last bit in the array, at each transition of the clock input.

In the simulation of all the figures below, the clock is set to 10 ns, so 80 ns mean 8 clock cycles. In Figure4 is reported a simulation of the serial to parallel converter VHDL code above. In order to realize the test bench, the parallel to serial converter of this post is used.

More generally, a shift register may be multidimensional, such that its 'data in' and stage outputs are themselves bit arrays; this is implemented simply by running several shift registers of the same bit-length in parallel.

Shift registers can have both parallel and serial inputs and outputs. These are often configured as 'serial-in, parallel-out' (SIPO) or as 'parallel-in, serial-out' (PISO). There are also types that have both serial and parallel input and types with serial and parallel output. There are also 'bidirectional' shift registers which allow shifting in both directions: L→R or R→L. The serial input and last output of a shift register can also be connected to create a 'circular shift register'. A PIPO register (parallel in, parallel out) is very fast – an output is given within a single clock pulse.

Serial-in serial-out (SISO)[edit]

Destructive readout[edit]

These are the simplest kind of shift registers. The data string is presented at 'Data In', and is shifted right one stage each time 'Data Advance' is brought high. At each advance, the bit on the far left (i.e. 'Data In') is shifted into the first flip-flop's output. The bit on the far right (i.e. 'Data Out') is shifted out and lost.

The data is stored after each flip-flop on the 'Q' output, so there are four storage 'slots' available in this arrangement, hence it is a 4-bit Register. To give an idea of the shifting pattern, imagine that the register holds 0000 (so all storage slots are empty). As 'Data In' presents 1,0,1,1,0,0,0,0 (in that order, with a pulse at 'Data Advance' each time—this is called clocking or strobing) to the register, this is the result. The right hand column corresponds to the right-most flip-flop's output pin, and so on.

So the serial output of the entire register is 00001011. It can be seen that if data were to be continued to input, it would get exactly what was put in (10110000), but offset by four 'Data Advance' cycles. This arrangement is the hardware equivalent of a queue. Also, at any time, the whole register can be set to zero by bringing the reset (R) pins high.

This arrangement performs destructive readout - each datum is lost once it has been shifted out of the right-most bit.

Serial-in parallel-out (SIPO)[edit]

This configuration allows conversion from serial to parallel format. Data input is serial, as described in the SISO section above. Once the data has been clocked in, it may be either read off at each output simultaneously, or it can be shifted out.

In this configuration, each flip-flop is edge triggered. All flip-flops operate at the given clock frequency. Each input bit makes its way down to the Nth output after N clock cycles, leading to parallel output.

Go to settings to activate windows. In cases where the parallel outputs should not change during the serial loading process, it is desirable to use a latched or buffered output. In a latched shift register (such as the 74595) the serial data is first loaded into an internal buffer register, then upon receipt of a load signal the state of the buffer register is copied into a set of output registers. In general, the practical application of the serial-in/parallel-out shift register is to convert data from serial format on a single wire to parallel format on multiple wires.

Parallel-in serial-out (PISO)[edit]

This configuration has the data input on lines D1 through D4 in parallel format, D1 being the most significant bit. To write the data to the register, the Write/Shift control line must be held LOW. To shift the data, the W/S control line is brought HIGH and the registers are clocked. The arrangement now acts as a PISO shift register, with D1 as the Data Input. However, as long as the number of clock cycles is not more than the length of the and 'shift left' the data in a register, effectively dividing by two or multiplying by two for each place shifted.

Very large serial-in serial-out shift registers (thousands of bits in size) were used in a similar manner to the earlier delay line memory in some devices built in the early 1970s. Such memories were sometimes called 'circulating memory'. For example, the Datapoint 3300 terminal stored its display of 25 rows of 72 columns of upper-case characters using fifty-four 200-bit shift registers, arranged in six tracks of nine packs each, providing storage for 1800 six-bit characters. The shift register design meant that scrolling the terminal display could be accomplished by simply pausing the display output to skip one line of characters.^[1]

History[edit]

One of the first known examples of a shift register was in the Mark 2 Colossus, a code-breaking machine built in 1944. It was a six-stage device built of vacuum tubes and thyratrons.^[2] A shift register was also used in the IAS machine, built by John von Neumann and others at the Institute for Advanced Study in the late 1940s.

See also[edit]

• Linear feedback shift register (LFSR)
• SerDes (Serializer/Deserializer)
• Shift register lookup table (SRL)

References[edit]

1. ^bitsavers.org, DataPoint 3300 Maintenance Manual, December 1976.
2. ^Flowers, Thomas H. (1983), 'The Design of Colossus', Annals of the History of Computing, 5 (3): 246, doi:10.1109/MAHC.1983.10079